Power Estimation for Sequential Logic Circuits

Recently developed methods for power estimation have primarily focused on combinational logic. In this paper, we present a framework for the eecient and accurate estimation of average power dissipation in sequential circuits. Switching activity is the primary cause of power dissipation in CMOS circuits. Accurate switching activity estimation for sequential circuits is considerably more diicult than that for combinational circuits, because the probability of the circuit being in each of its possible states has to be calculated. The Chapman-Kolmogorov equations can be used to compute the exact state probabilities in steady state. However, this method requires the solution of a linear system of equations of size 2 N where N is the number of ip-ops in the machine. In this paper, we describe a comprehensive framework for exact and approximate switching activity estimation in a sequential circuit. The basic computation step is the solution of a non-linear system of equations which is derived directly from a logic realization of the sequential machine. Increasing the number of variables or the number of equations in the system results in increased accuracy. For a wide variety of examples, we show that the approximation scheme is within 1 ?3% of the exact method, but is orders of magnitude faster for large circuits. Previous sequential switching activity estimation methods can have signiicantly greater inaccuracies.